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POWER MANAGEMENT Description
The SC488 is a combination switching regulator and linear source/sink regulator intended for DDR1/2 memory systems. The purpose of the switching regulator is to generate the supply voltage, VDDQ, for the memory system. It is a pseudo-fixed frequency constant on-time controller designed for high efficiency, superior DC accuracy, and fast transient response. The purpose of the linear source/sink regulator is to generate the memory termination voltage, VTT, with the ability to source and sink 2.8A peak currents. For the VDDQ regulator, the switching frequency is constant until a step in load or line voltage occurs at which time the pulse density, i.e., frequency, will increase or decrease to counter the transient change in output or input voltage. After the transient, the frequency will return to steady-state operation. At lighter loads, the selectable Power-Save Mode enables the PWM converter to reduce its switching frequency and improve efficiency. The integrated gate drivers feature adaptive shoot-through protection and softswitching. Additional features include cycle-by-cycle current limiting, digital soft-start, over-voltage and under-voltage protection and a power good flag. For the VTT regulator, the output voltage tracks REF, which is 1/2 VDDQ to provide an accurate termination voltage. The VTT output is generated from a 1.2V to VDDQ input by a linear source/sink regulator which is designed for high DC accuracy, fast transient response, and low external component count. All three outputs (VDDQ, VTT and REF) are actively discharged when VDDQ is disabled, reducing external component count and cost. The SC488 is available in a 24-pin MLPQ (4x4 mm) package.
Complete DDR1/2/3 Memory Power Supply
Features
Constant On-Time Controller for Fast Dynamic Response on VDDQ DDR1/DDR2/DDR3 Compatible VDDQ = Fixed 1.8V or 2.5V, or Adjustable From 1.5V to 3.0V 1.5% Internal Reference (2.5% System Accuracy) Resistor Programmable On-Time for VDDQ VCCA/VDDP Range = 4.5V to 5.5V VIN Range = 2.5V to 25V VDDQ DC Current Sense Using Low-Side RDS(ON) Sensing External RSENSE in Series with Low-Side FET Cycle-by-Cycle Current Limit for VDDQ Digital Soft-Start for VDDQ Analog Soft-Start for VTT/REF Smart Over-Voltage VDDQ Protection Combined EN and PSAVE Pin for VDDQ Over-Voltage/Under-Voltage Fault Protection Power Good Output Separate VCCA and VDDP Supplies VTT/REF Range = 0.75V - 1.5V VTT Source/Sink 2.8A Peak Internal Resistor Divider for VTT/REF VTT is High Impedance in S3 VDDQ, VTT, REF are Actively Discharged in S4/S5 24 Lead MLPQ (4x4 mm) Lead-Free Package Product Is Fully WEEE and RoHS Compliant
SC488
Applications
Notebook Computers CPU I/O Supplies Handheld Terminals and PDAs LCD Monitors Network Power Supplies
C2 0.1uF Q1 VBAT C3 2x10uF
Typical Application Circuit
5V VDDQ VTT VBAT C4 10uF C5 10uF C1 1uF 1 2 VTTSNS 3 4 C7 1nF R6 10R REF C9 1uF C8 0.1uF C10 1uF 5 6 D1
24
23
22
21
20
19
LX
BST
DL
VTT
L1 Q2 18 17 16 15 14 13 PAD R4 R7 10R C11 1uF RILIM C6
VDDQ +
PGND2 VTTS VSSA TON REF
VTTIN
DH
PGND1 U1 PGND1 ILIM VDDP VDDP
R1 1Meg
SC488
VDDQS
VTTEN
EN/PSV
VCCA
NC
PGD
NC
PGOOD
FB
PAD
10
11
12
7
8
9
5V
VDDQ
EN/PSV VTT_EN
September 28, 2006
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SC488
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
Parameter TON to VSSA DH, BST to PGND1 BST, DH to LX LX to PGND1 DL, ILIM, VDDP to PGND1 VDDP to DL VTTIN to PGND2; VTT to PGND2; VTTIN to VTT EN/PSV, FB, PGD, REF, VCCA, VDDQS, VTTEN, VTTS to VSSA VCCA to EN/PSV, FB, REF, VDDQS, VTT, VTTEN, VTTIN, VTTS PGND1 to PGND2; PGND1 to VSSA; PGND2 to VSSA Thermal Resistance Junction to Ambient(1) Operating Junction Temperature Range Storage Temperature Range Peak IR Reflow Temperature, 10s - 40s ESD Protection Level(2)
Symbol
Maximum -0.3 to +25.0 -0.3 to +31.0 -0.3 to +6.0 -2.0 to +25.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +0.3
Units V V V V V V V V V V C/W C C C kV
JA TJ TSTG TPKG VESD
29 -40 to +150 -65 to +150 260 2
Notes: 1) Calculated from package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. 2) Tested according to JEDEC standard JESD22-A114-B.
Electrical Characteristics
Test Conditions: VIN = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, RTON = 1M. TAMB = -40 TO +85C.
25C Parameter Conditions Min Input Supplies VCCA Operating Current VCCA Operating Current VCCA Operating Voltage VDDP Operating Current TON Operating Current VTTIN Operating Current VCCA + VDDP + TON Shutdown Current VTTIN Shutdown Current FB > Regulation Point, IVDDQ = 0A RTON = 1M IVTT = 0A EN/PSV = VTTEN = 0V EN/PSV = VTTEN = 0V S0 State (VTT on); EN/PSV = VCCA; FB > Regulation Point, IVDDQ = 0A S3 State (VTT off); EN/PSV = VCCA; FB > Regulation Point, IVDDQ = 0A 1500 800 5 70 15 1 5 1 Typ Max
-40C to 85C Units Min Max
2500 1400 4.5 5.5 150
A A V A A
5 22
A A A
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SC488
POWER MANAGEMENT Electrical Characteristics (Cont.)
25C Parameter Conditions Min VDDQ Controller FB Error Comparator Threshold(1) VDDQS Regulation Threshold With Adjustable Resistor Divider FB = AGND FB = VCCA RTON = 1M, VDDQ = 1.8V RTON = 500k, VDDQ = 1.8V 1.500 2.5 1.8 460 265 400 FB < 0.3V FB > 0.3V EN/PSV = GND 80 91 16 -1.0 8 1.0 1.4775 2.4625 1.773 368 212 1.5225 2.5375 1.827 552 318 550 V V V ns ns k A % Typ Max Min Max -40C to 85C Units
On-Time Minimum Off-Time VDDQS Input Resistance VDDQS Shutdown Discharge Resistance FB Leakage Current VDDQ Smart Psave Threshold VTT Controller REF Source Current REF Sink Resistance REF Output Accuracy Shutdown Discharge Resistance (EN/PSV = GND) VTT Output Accuracy (with respect to REF) VTTS Leakage Current Current Sensing ILIM Current Current Comparator Offset Zero-Crossing Threshold VDDQ Fault Protection
10 50 IREF = 0 to 10mA VTT REF -2A < IVTT < 2A(9) 900 0.32 8 0 -40 -1.0 +40 1.0 882 918
mA k mV
mV A
DL High PGND1 - ILIM PGND1 - LX, EN/PSV = 5V
10
9 -10
11 10
A mV mV
5
PGND1 - LX, RLIM = 5k Current Limit (Positive)(2) PGND1 - LX, RLIM = 10k PGND1 - LX, RLIM = 20k Current Limit (Negative) Output Under-Voltage Fault PGND1 - LX With Respect to FB Regulation Point
50 100 200 -125 -30
35 80 170 -160 -35
65 120 230 -90 -25 mV % mV
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SC488
POWER MANAGEMENT Electrical Characteristics (Cont.)
25C Parameter Conditions Min VDDQ Fault Protection (continued) Under-Voltage Fault Delay Under-Voltage Blank Time Output Over-Voltage Fault Over-Voltage Fault Delay PGD Low Output Voltage PGD Leakage Current PGD UV Threshold PGD Fault Delay VCCA Under-Voltage (UVLO) VTT Fault Protection UV Lower Threshold OV Upper Threshold Fault Shutdown Delay Thermal Shutdown(4)(5) Inputs/Outputs Logic Input Low Voltage EN/PSV Low/Low (Disabled) VTTEN Low (VTT Disabled) EN/PSV Low/High (Enabled, Psave Disabled) VTTEN High (VTT Enabled) Logic Input High Voltage EN/PSV Input Resistance VTTEN Leakage Current Soft-Start VDDQ Soft-Start Ramp Time VTT Soft-Start Ramp Rate(6) FB Input Thresholds FB Logic Input Low FB Logic Input High VDDQ Set for 2.5V (DDR1) VDDQ Set for 1.8V (DDR2) 0.3 VCCA - 0.7 V V EN/PSV High to PGD High 440 5.5 clks(3) mV/s EN/PSV High/High (Enabled, Psave Enabled) Sourcing Sinking 1.5 1.0 -1 +1 1.2 2.4 3.1 V M A 1.2 0.6 2.4 V VTT w/rt REF VTT w/rt REF VTT Outside OV/UV Window -12 +12 50 160 150 170 -16 +8 -8 +16 % % s C FB Forced Below UV VTH From EN High With Respect to FB Regulation Point FB Above Over-Voltage Threshold Sink 1mA FB in Regulation, PGD = 5V With Respect to FB Regulation Point FB Forced Outside PGD Window Falling Edge (Hysteresis 100 mV) -10 5 4 3.70 4.35 -12 8 440 +16 5 0.1 1 -8 +12 +20 clks(3) clks(3) % s V A % s V Typ Max Min Max -40C to 85C Units
Logic Input High Voltage
V
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SC488
POWER MANAGEMENT Electrical Characteristics (Cont.)
25C Parameter Conditions Min Gate Drives Shoot-Thru Protection Delay(4)(7) DL Pull-Down Resistance DL Sink Current DL Pull-Up Resistance DL Source Current DH Pull-Down Resistance DH Pull-Up Resistance(8) DH Sink/Source Current VTT Pull-Up Resistance VTT Pull-Down Resistance VTT Peak Sink/Source Current(9) DH or DL Rising DL Low VDL = 2.5V DL High VDL = 2.5V DH Low, BST - LX = 5V DH High, BST - LX = 5V VDH = 2.5V VTTS < REF VTTS > REF 30 0.8 3.1 2 1.3 2 2 1.3 0.25 0.32 2.8 ns A A A A Typ Max Min Max -40C to 85C Units
Notes: 1) The VDDQ DC regulation level is higher than the FB error comparator threshold by 50% of the ripple voltage. 2) Using a current sense resistor, this measurement relates to PGND1 minus the source of the low-side MOSFET. 3) clks = switching cycles, consisting of one high side and one low side gate pulse. 4) Guaranteed by design. 5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset. 6) VTT soft-start ramp rate is limited to 5.5mV/s typical. If the VDDQ/2 ramp rate is slower than 5.5mV/sec, the VTT soft-start ramp will follow the VDDQ/2 ramp. 7) See Shoot-Through Delay Timing Diagram below. 8) Semtech's SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10 (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device is activated, reducing the resistance to 2 (typical). This creates a softer turn-on with minimal power loss, eliminating the need for an external gate or boost resistor. 9) Provided operation below TJ(MAX) is maintained. VTT output current is also limited by internal MOSFET resistance which is typically 0.32 at 25C and which increases with temperature, and by available source voltage (typically VDDQ/2).
Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL
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tplhDH
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SC488
POWER MANAGEMENT Pin Configuration
SC488 MLP24 Pin Out SC480
VTTIN BST VTT DH DL LX
Ordering Information
Device(2) SC488MLTRT Package(1) MLPQ-24
PGND2 VTTS VSSA TON REF VCCA
1 2 3 4 5 6
18 17 16
PGND1 PGND1 ILIM VDDP VDDP PGD
Notes: 1) Only available in tape and reel packaging. A reel contains 3000 devices. 2) This product is fully WEEE and RoHS compliant.
23
22
21
20
T
19
15 14 13
24
10
EN/PSV
VDDQS
VTTEN
NC
FB
11
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 Pin Name PGND2 VTTS VSSA TON REF VCCA NC VDDQS FB VTTEN Pin Function Power ground for VTT output. Connect to thermal pad and ground plane. Sense pin for VTT. Connect to VTT at the load. Ground reference for analog circuitry. Connect to thermal pad. This pin is used to sense VBAT through a pull-up resistor, RTON, which sets the top MOSFET on-time. Bypass this pin with a 1nF capacitor to VSSA. Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ (nominal). Bypass this pin with a series 10/1F to VSSA. Analog supply voltage input. Use a 10/1F RC filter from +5V to VSSA. No connect. Sense input for VDDQ. Used to set the on-time for the top MOSFET and also to set REF/VTT. Feedback select input for VDDQ. See FB Configuration Table. Enable pin for VTT. Pull this pin low to disable VTT (REF remains present as long as VDDQ is present). Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If floated, bypass to VSSA with a 10nF capacitor. No connect. Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This pin is an open drain NMOS output and requires an external pull-up resistor.
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11 12 13
EN/PSV NC PGD
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NC
12
7
8
9
SC488
POWER MANAGEMENT Pin Description (Cont.)
14,15 16 17,18 19 20 21 22 23 24 T VDDP ILIM PGND1 DL LX DH BST VTTIN VTT THERMAL PAD +5V supply voltage input for the VDDQ gate drivers. Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. Power ground for VDDQ switching circuits. Connect to thermal pad and ground plane. Gate drive output for the low side MOSFET switch. Phase node - the junction between the top and bottom FETs and the output inductor. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Input supply for the high side switch for VTT regulator. Decouple with a 1F capacitor to PGND2. Output of the linear regulator. Decouple with two (minimum) 10F ceramic capacitors to PGND2, locating them directly across pins 24 and 1. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
Enable Control Logic
Enable Pin Status EN/PSV (1) 0 0 1 1 VTTEN 0 1 0 1 VDDQ(3) OFF, Discharged OFF, Discharged ON ON
(2)(3)
Output Status VTT(2) OFF, Discharged OFF, Discharged
(2)
REF(2) OFF, Discharged OFF, Discharged ON ON
(2) (2)
(2)(3)
(2)
OFF, High Impedance ON
Notes: 1) EN/PSV = 1 = EN/PSV high or floating. 2) Typical discharge resistances: VTT = 0.32. REF = 8. 3) VDDQ is discharged via external series resistance which must be added to SC488 internal discharge resistance to calculate discharge times. This is separate from any external load on VDDQ.
FB Configuration Table
The FB pin can be configured for fixed or adjustable output voltage as shown.
FB GND VCCA FB Resistors
VDDQ(V) 2.5 1.8 Adjustable
VREF & VTT (V) VDDQS/2 VDDQS/2 VDDQS/2
Note DDR1 DDR2 1.5V < VDDQ < 3.0V
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SC488
POWER MANAGEMENT Block Diagram
VTTEN VCCA OTSD VDDQS POR/SS
VTTIN
DRVH
+12%
NOVLP
VTT
DRVL -12%
PGND2
REF
DSCHG DRVH
FEDLY VCCA EN/ PSV TON
+12% DRVL
VTTRUN OTSD TON/ TOFF
VTTPGD
VTTS
POR/SS VDDQS
VDDQS DSCHG
DSCHG -12%
BST
HI
-10% +16% -30%
1.5V REF
DH LX VDDP
VMON
OV SD
CONTROL
LX DL
SHOOT THRU
LO 1.5V
DL
PGND1 FB
PWM
-10%
SENSE
UV
-30% SD
ILIM PGD
OV +16%
FAULTMON
VSSA
Figure 1
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SC488
POWER MANAGEMENT Application Information
+5V Bias Supplies The SC488 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator. To minimize crosstalk, the controller has seven supply pins: VDDP (2 pins), PGND1 (2 pins), PGND2, VCCA and AGND. The controller requires its own AGND plane which should be tied by a single trace to the negative terminal of the output capacitor. All external components referenced to AGND in the schematic should then be connected to the AGND plane. The supply decoupling capacitor should be tied between VCCA and AGND. A single 10 resistor should be used to decouple the VCCA supply from the main VDDP supply. PGND can then be a separate plane which is not used for routing analog traces. All PGND connections should connect directly to this plane with special attention given to avoiding indirect connections between AGND and PGND which will create ground loops. As mentioned above, the AGND plane must be connected to the PGND plane at the negative terminal of the output capacitor. The VDDP input provides power to the upper and lower gate drivers. A decoupling capacitor for the VDDP supply and PGND is recommended. No series resistor between VDDP and the 5 volt bias is required. Pseudo-Fixed Frequency Constant On-Time PWM Controller The PWM control method is a constant-on-time, pseudofixed frequency PWM controller, see Figure 1. The ripple voltage seen across the output capacitor's ESR provides the PWM ramp signal, eliminating the need for a current sense resistor. The on-time is determined by a one-shot whose period is proportional to output voltage, and inversely proportional to input voltage. A separate one-shot sets the minimum off-time (typically 425ns). On-Time One-Shot (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a proportional current. This current charges an internal on-time capacitor. The TON time is the time required for this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator.
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TON
3.3x10 12 (RTON 37x10 3 )
VOUT VIN
50ns
RTON is a resistor connected between the input supply and the TON pin. VDDQ/VTT Enable & Power-Save The EN/PSV pin controls the VDDQ supply and the REF output (1/2 of VDDQ). VTTEN enables the VTT supply. The VTT and VDDQ supplies may be enabled independently. When EN/PSV is tied to VCCA the VDDQ controller is enabled in power-save mode. When the EN/PSV pin is floated, an internal resistor divider activates the VDDQ controller with power-save disabled. If PSAVE is enabled, the SC488 PSAVE comparator looks for inductor current to cross zero on eight consecutive cycles. Once observed, the controller enters power-save and turns off the low-side MOSFET when the current crosses zero. To improve the efficiency and add hysteresis, the on-time is increased by 20% in powersave. The efficiency improvement at light loads more than offsets the disadvantage of slightly higher output ripple. If the inductor current does not cross zero on any switching cycle, the controller immediately exits power-save. Since the controller counts zero crossings, the converter can sink current as long as the current does not cross zero on eight consecutive cycles. This allows the output voltage to recover quickly in response to negative load steps even when power-save is enabled. VDDQ Voltage Selection VDDQ voltage is set using the FB pin. Grounding FB sets VDDQ to fixed 2.5V. Connecting FB to +5V sets VDDQ to fixed 1.8V. VDDQ can also be adjusted from 1.5 to 3.0V using external resistors, see Figure 2. The voltage at FB is then compared to the internal 1.5V reference.
To VDDQ output capacitor
R2
C
To SC488 FB (pin 9)
R3
Figure 2
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SC488
POWER MANAGEMENT Application Information
Referencing Figure 2, the equation for setting the output voltage is: The schematic of RDSON sensing circuit is shown in Figure 4 with RILIM = R1 and RDSON of Q2.
+5V +VIN
Vout
1 + R2 1.5 R3
D1
+
C1
Current Limit Circuit Current limiting of the SC488 can be accomplished in two ways. The on-state resistance of the low-side MOSFETs can be used as the current sensing element, or a sense resistor in the low-side source can be used if greater accuracy is desired. RDSON sensing is more efficient and less expensive. In both cases, the RILIM resistor between the ILIM pin and LX sets the over-current threshold. This resistor RILIM is connected to a 10A current source within the SC488 which is turned on when the low-side MOSFET turns on. When the voltage drop across the sense resistor or low-side MOSFET equals the voltage across the RILIMresistor, current limit will activate. The high-side MOSFET will not be allowed to turn on until the voltage drop across the sense element (resistor or MOSFET) falls below the voltage across the RILIM resistor. The current sensing circuit actually regulates the inductor valley current, see Figure 3. This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current.
C2 BST DH LX ILIM VDDP DL PGND
Q1 L1 Vout
R1 Q2
D2
+
C3
SC488
Figure 4 Similarly, for resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an over-current exists and the high-side MOSFET will not be allowed to turn on. The over-current equation when using an external sense resistor is:
IL OC Valley 10 A RILIM RSENSE
Schematic of resistor sensing circuit is shown in Figure 5 with RILIM = R1 and RSENSE = R4.
+5V +VIN
INDUCTOR CURRENT
I PEAK
D1
+ C1
I LOAD
C2
Q1 L1 Vout
I LIMIT
BST DH LX ILIM VDDP DL PGND
D2 Q2
+ C3
SC488
TIME Valley Current - Limit Threshold Point
R1
R4
Figure 3
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Figure 5
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SC488
POWER MANAGEMENT Application Information (Cont.)
Power Good Output The VDDQ controller has a power good (PGD) output. Power good is an open-drain output and requires a pull-up resistor. When the output voltage is +16%/-10% from its nominal voltage, PGD gets pulled low. It is held low until the output voltage returns to within +16%/-10% of nominal. PGD is also held low during start-up and will not be allowed to transition high until soft-start is over and the output reaches 90% of its set voltage. There is a 5s delay built into the PGD circuit to prevent false transitions. Output Over-Voltage Protection When the VDDQ output exceeds 16% of its set voltage, the low-side MOSFET is latched on. It stays latched and the SMPS stays off until the EN/PSV input is toggled or VCCA is recycled. There is a 5s delay built into the OV protection circuit to prevent false transitions. During a VDDQ OV shutdown, VTT is alive until VDDQ falls to typically 0.4V, at which point VTT is tri-stated. When VTT exceeds 12% above its set voltage, the VTT regulator will tristate. There is a 50s delay to prevent false OV trips due to transients or noise. The VDDQ regulator continues to operate after VTT OV shutdown. The VTT OV condition is removed by toggling VTTEN or EN/PSV, or by recycling VCCA. Smart Over-Voltage Protection In some applications, the active loads on VDDQ can actually leak current into VDDQ. If PSAVE mode is enabled at very light loading, this leak can cause VDDQ to slowly rise and reach the OV threshold, causing a hard shutdown. To prevent this, the SC488 uses Smart OVP to prevent this. When VDDQ exceeds 8% above nominal, DL drives high to turn on the low-side MOSFET, which starts to draw current from VDDQ via the inductor. When VDDQ drops to the FB trip point, a normal TON switching cycle begins. This prevents a hard OV shutdown. Output Under-Voltage Protection When VDDQ falls 30% below its set point for eight clock cycles, the VDDQ output is shut off; the DL/DH drives are pulled low to tristate the MOSFETS, and the SMPS stays off until the Enable input is toggled or VCCA is recycled. When VTT is 12% below its set voltage the VTT output is tristated. There is a 50s delay for VTT built into the UV protection circuits to prevent false transitions. POR, UVLO and Soft-Start An internal power-on reset (POR) occurs when VCCA exceeds 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA under-voltage lockout (UVLO), circuitry inhibits switching and tristates the drivers until VCCA rises above 4.2V. At this time the circuit will come out of UVLO and begin switching and the softstart circuit will progressively limit the output current over a pre-determined time period. The ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. There is 100mV of hysteresis built into the UVLO circuit and when VCCA falls to 4.1V the output drivers are shutdown and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for moderate, highside, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off, and conversely, monitors the DH output and prevents the low side MOSFET from turning on until DH is fully off.
(Note: be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.)
Design Procedure Prior to designing a switch mode supply for a notebook computer, the input voltage, load current, switching frequency and inductor ripple current must be specified. Input Voltage Range The maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage. The minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. Maximum Load Current There are two values of load current to consider: continuous load current and peak load current. Continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, MOSFETs and commutation diodes. Peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit.
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SC488
POWER MANAGEMENT Application Information (Cont.)
Switching Frequency Switching frequency determines the trade-off between size and effi ciency. Higher frequency increases switching losses in the MOSFETs, since losses are a function of F*VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates the final design. Inductor Ripple Current Low inductor values result in smaller size, but create higher ripple current and are less efficient because of the high AC current flowing in the inductor. Higher inductor values do reduce the ripple current and are more efficient, but are larger and more costly. The selection of the ripple current is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. Again, cost, size and efficiency all play a part in the selection process. Stability Considerations Unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is too low, causing insufficient voltage ramp in the output signal. This causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. In some cases, however, double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. Another way to eliminate doubling-pulsing is to add a 10pF capacitor across the upper feedback resistor divider network. This is shown in Figure 6, by capacitor C4 in the schematic. This capacitance should be left out until confirmation that double-pulsing exists. Adding this capacitance will add a zero in the transfer function and should eliminate the problem. It is best to leave a spot on the PCB in case it is needed. Loop instability can cause oscillations at the output as a response to line or load transients. These oscillations can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit.
BST DH LX ILIM VDDP DL PGND +5V +VIN
D1
+
C1
14 13 12 11 10 9 8
C2
Q1 L1 0.5V - 5.5V
R1 D2 Q2 + C3
R2
C4 10pF
SC488
R3 FBK
Figure 6 The best way for checking stability is to apply a zero to full load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ringing after the initial step is a sign that the ESR should be increased. SC488 ESR Requirements The constant on-time control used in the SC488 regulates the ripple voltage at the output capacitor. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors, the absolute minimum ESR must be considered. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. Referring to Figure 5 on Page 10, the equation for the minimum ESR as a function of output capacitance and switching frequency and duty cycle is:
ESR
VOUT 1.5V
1 2
3
Fs - 200000 Fs 1D 2
Cout Fs
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SC488
POWER MANAGEMENT Application Information (Cont.)
Dropout Performance The output voltage adjust range for continuous-conduction operation is limited by the fi xed 400nS (typical) Minimum Off-time One-shot. For best dropout performance, use the slowest on-time setting of 200KHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC dutyfactorlimitation is given by:
DUTY TON (MIN) TON (MIN) TOFF (MAX)
of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contributes additional error. If tighter DC accuracy is required use 0.1% feedback resistor. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage (it will not change the frequency). Switching frequency variation with load can be minimized by choosing lower RDSON MOSFETs. High RDSON MOSFETS will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. This inherent droop should be considered when deciding if passive droop is required, or if passive droop is desired in order to further reduce the output capacitance. Output DC Accuracy (VTT Output) The VTT accuracy compared to VDDQ is determined by two parameters: the REF output accuracy, and the VTT output accuracy with respect to REF. The REF output is generated internally from the VDDQS (sense input), and tracks VDDQS with 2% accuracy. This REF output becomes the reference for the VTT regulator. The VTT regulator then tracks REF within +/-40mV (typically zero). The total VTT/VDDQ tracking accuracy is then:
VTT error VDDQS 2 0.02 40mV
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. SC488 System DC Accuracy (VDDQ Controller) Three IC parameters affect VDDQ accuracy: the internal 1.5V reference, the error comparator offset voltage, and the switching frequency variation with line and load. The internal 1.5%, 1.5V reference contains two error components, a 0.5% DC error and a 0.5% supply and temperature error. The error comparator offset is trimmed so that it trips when the feedback pin is nominally 1.5 volts +/-1.5% at room temperature. The comparator offset trim compensates for any DC error in the reference. Thus, the percentage error is the sum of the reference variation over supply and temperature and the offset in the error comparator, or 2.0% total. The on-time pulse in the SC488 is calculated to give a pseudo-fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on-time converters regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, If the output ripple is 50mV with VIN = 6 volts, then the measured DC output will be 25mV above the comparator trip point. If the ripple increases to 80mV with VIN = 25 volts, then the measured DC output will be 40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation it is often desirable to use passive droop. Take the feedback directly from the output side of the inductor, incorporating a small amount
DDR Reference Buffer The reference buffer is capable of sourcing 10mA. The reference buffer has a class A output stage and therefore will not sink significant current; there is an internal 50 k (typical) pulldown to ground. If higher current sinking is required, an external pulldown resistor should be added. Make sure that the ground side of this pulldown is tied to the VTT ground plane near the PGND2 pin.
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SC488
POWER MANAGEMENT Application Information (Cont.)
For stability, place a 10/1F series combination from REF to VSSA. If REF load capacitance exceeds 1F, place at least 10's in series with the load capacitance to prevent instability. It is possible to use only one 10 resistor, by connecting the load capacitors in parallel with the 1F, and connecting the load REF to the capacitor side of the 10 resistor. (See the Typical Application Circuit on Page 1.) Note that this resistor creates an error term when REF has a DC load. In most applications this is not a concern since the DC load on REF is negligible. Design Procedure Prior to designing a switching output and making component selections, it is necessary to determine the input voltage range and output voltage specifications. To demonstrate the procedure, the output for the schematic in Figure 7 on page 19 will be designed. The maximum input voltage (VBAT(MAX)) is determined by the highest AC adaptor voltage. The minimum input voltage (VBAT(MIN)) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. For the purposes of this design example we will use a VBAT range of 8V to 20V to design VDDQ. Four parameters are needed for the design: 1. Nominal output voltage, VOUT. We will use 1.8V with internal feedback resistors (FB pin tied to VCCA). 2. Static (or DC) tolerance, TOLST (we will use +/-2%). 3. Transient tolerance, TOLTR and size of transient (we will use +/-8% for a 10A to 5A load release for this demonstration). 4. Maximum output current, IOUT (we will design for 10A). Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, and losses are a function of VBAT2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. The default RtON values of 1M and 715k are suggested only as a starting point. The first thing to do is to calculate the on-time, tON, at VBAT(MIN) and VBAT(MAX), since this depends only upon VBAT, VOUT and RtON.
t ON_VBAT(MIN) 3.3 10 12 R tON 37 10 3 VOUT VBAT(MIN) 50 10 9 s
and,
t ON_VBAT(MAX) 3.3 10 12 R tON 37 10 3 VOUT VBAT(MAX) 50 10 9 s
From these values of tON we can calculate the nominal switching frequency as follows:
f SW_VBAT (MIN) VOUT VBAT(MIN) t ON_VBAT(MIN) Hz
and,
f SW_VBAT (MAX) VOUT VBAT(MAX) t ON_VBAT(MAX) Hz
tON is generated by a one-shot comparator that samples VBAT via RtON, converting this to a current. This current is used to charge an internal 3.3pF capacitor to VOUT. The equations above reflect this along with any internal components or delays that influence tON. For our example we select RtON = 1M: tON_VBAT(MIN) = 820ns and, tON_VBAT(MAX) = 358ns fSW_VBAT(MIN) = 274kHz and fSW_VBAT(MAX) = 251kHz Now that we know tON we can calculate suitable values for the inductor. To do this we select an acceptable inductor ripple current. The calculations below assume 50% of IOUT which will give us a starting place.
L VBAT(MIN) VBAT(MIN) VOUT t ON_VBAT (MIN) 0.5 IOUT H
and,
L VBAT (MAX) VBAT(MAX) VOUT t ON_VBAT(MAX) 0.5 IOUT H
For our example, LVBAT(MIN) = 1.02H and LVBAT(MAX) = 1.30H,
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SC488
POWER MANAGEMENT Application Information (Cont.)
We will select an inductor value of 1.5H to reduce the ripple current, which can be calculated as follows:
t ON_ VBAT ( MIN ) L
RESR_ST(MAX) = 8.3m
ERRTR ERRDC Ohms IRIPPLE_VBAT( MAX ) I TRANS 2
I RIPPLE_VBAT( MIN )
VBAT (MIN )
V OUT
AP P
R ESR_ TR ( MAX)
and,
I RIPPLE_VBAT( MAX ) VBAT (MAX ) V OUT t ON_ VBAT ( MAX ) AP P L
where ERRTR is the transient output tolerance. For this case, ITRANS is the load transient of 5A (10A - 5A). For our example:
For our example: IRIPPLE_VBAT(MIN) = 3.39AP-P and IRIPPLE_VBAT(MAX) = 4.34AP-P From this we can calculate the minimum inductor current rating for normal operation:
I INDUCTOR ( MIN ) I OUT ( MAX ) I RIPPLE_VBAT ( MAX ) A (MIN) 2
ERRTR = 144mV and ERRDC = 18mV, therefore, RESR_TR(MAX) = 17.6m for a full 5A load transient. We will select a value of 6m maximum for our design, which would be achieved by using two 12m output capacitors in parallel. Now that we know the output ESR we can calculate the output ripple voltage:
V RIPPLE_VBAT ( MIN ) R ESR I RIPPLE_VBAT ( MIN ) VP P
For our example: IINDUCTOR(MIN) = 12.2A(MIN) Next we will calculate the maximum output capacitor equivalent series resistance (ESR). This is determined by calculating the remaining static and transient tolerance allowances. Then the maximum ESR is the smaller of the calculated static ESR (RESR_ST(MAX)) and transient ESR (RESR_TR(MAX)):
ERR ST ERR DC 2
and,
V RIPPLE_VBAT ( MAX ) R ESR IRIPPLE_VBAT ( MAX ) VP P
For our example: VRIPPLE_VBAT(MAX) = 20mVP-P and VRIPPLE_VBAT(MIN) = 26mVP-P Note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, VFB, should be approximately 15mVP-P at minimum VBAT, and worst case no smaller than 10mVP-P. Note that the voltage ripple at FB is smaller than the voltage ripple at the output capacitor, due to the resistor divider. Also, when using internal feedback (FB pin tied to 5V or GND), the FB resistor divider is actually inside the IC. If VRIPPLE_VBAT(MIN) as seen at the FB point is less than 15mVP-P - whether internal or external FB is used - the above component values should be revisited in order to improve this. For our example, since the internal divider reduces the ripple signal by a factor of (1.5V/1.8V), the internal FB ripple values are then 17mV and 22mV, which is above the 15mV minimum.
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R ESR _ ST ( MAX )
I RIPPLE _ V BAT ( MAX )
Ohms
Where ERRST is the static output tolerance and ERRDC is the DC error. The DC error will be 1% plus the tolerance of the internal feedback. (Use 2% for external feedback which is 1% plus another 1% for the external resistors.) For our example: ERRST = 36mV and, ERRDC = 18mV, therefore,
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SC488
POWER MANAGEMENT Application Information (Cont.)
When using external feedback, and with VDDQ greater than 1.5V, a small capacitor, CTOP, can be used in parallel with the top feedback resistor, RTOP, in order to ensure that ripple at VFB is large enough. CTOP should not be greater than 100pF. The value of CTOP can be calculated as follows, where RBOT is the bottom feedback resistor. Firstly calculating the value of ZTOP required:
Z TOP RBOT 0.015 V RIPPLE_VBAT (MIN ) 0.015 Ohms
C OUT(MIN) L
The minimum output capacitance is calculated as follows:
Iinit I OUT ( MAX ) IRIPPLE_VBAT ( MAX ) 2 A
and,
Iinit 2 Ifinal 2 POSLIMTR2 VOUT_ST_POS2
F
Secondly calculating the value of CTOP required to achieve this:
1 C TOP Z TOP 2 1
RTOP F f SW _ VBAT ( MIN )
This calculation assumes the condition of a full-load to noload step transient occurring when the inductor current is at its highest. The capacitance required for smaller transient steps my be calculated by substituting the desired current for the Ifinal term. In this case Ifinal is set for 5A. For our example:
Since our example uses internal feedback ,this method cannot be used, however the voltage seen at the internal FB point is already greater than 15mV. Next we need to calculate the minimum output capacitance required to ensure that the output voltage does not exceed the transient maximum limit, POSLIMTR, starting from the actual static maximum, VOUT_ST_POS, when a load release occurs:
V OUT_ST_POS V OUT ERR DC V
COUT(MIN) = 392F. We will select 440F, using two 220F, 12m capacitors in parallel. Next we calculate the RMS input ripple current, which is largest at the minimum battery voltage:
IOUT A RMS VBAT _ MIN
For our example: VOUT_ST_POS = 1.818V,
POSLIM TR V OUT TOL TR V
I IN ( RMS )
V OUT
VBAT ( MIN )
VOUT
For our example:
IIN(RMS) = 4.17ARMS
Input capacitors should be selected with sufficient ripple current rating for this RMS current, for example a 10F, 1210 size, 25V ceramic capacitor can handle approximately 3ARMS. Refer to manufacturer's data sheets and derate appropriately.
Where TOLTR is the transient tolerance. For our example: POSLIMTR = 1.944V,
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SC488
POWER MANAGEMENT Application Information (Cont.)
Finally, we calculate the current limit resistor value. As described in the current limit section, the current limit looks at the "valley current", which is the average output current minus half the ripple current.
I VALLEY IOUT IRIPPLE_VBAT( MIN ) 2 A
is always VDDQ2, regardless of whether the regulator is sinking or sourcing current. In either case the power lost in the VTT regulator is VTT * |ITT|. The average or long-term value for ITT should be used. The thermal resistance of the MLPQ package is affected by PCB layout and the available ground planes and vias which conduct heat away. A typical value is 29C/watt. Example: ICCA = 1.5mA IDDP = 25mA VCCA = VDDP = 5V VTT = 1.25V ITT = 0.75A (average) Ambient = 45 degrees C Thermal resistance = 29
The ripple at low battery voltage is used because we want to make sure that current limit does not occur under normal operating conditions.
R ILIM IVALLEY 1.2 R DS (ON) 1.4 10 10 6 Ohms
PD = 5V * 0.0015 A + 5V * 0.025A + 0.9V * |0.75|A
For our example: IVALLEY = 8.31A, RDS(ON) = 4m, giving RILIM = 5.62k Thermal Considerations The junction temperature of the device may be calculated as follows: TJ = TAMB + JA where TJ is the junction temperature, TAMB is the ambient temperature, PD is the total SC488 device dissipation. The SC488 device dissipation can be determined using: PD = VCCA * ICCA + VDDP * IDDP + VTT * |ITT| The fi rst two terms are losses for the analog and gate drive circuits and generally do not present a thermal problem. Typical ICCA (VCCA operating current) is roughly 1.5mA, which creates 7.5mW loss from the 5V VCCA supply. The VDDP supply current is used to drive the MOSFETs and can be much higher, on the order of 30mA, which can create up to 150mW of dissipation. The last term, VTT * |ITT|, is the most signifi cant term from a thermal standpoint. The VTT regulator is a linear device and will dissipate power proportional to the VTT current and the voltage drop across the regulator. If VTT = VDDQ/2, then the voltage drop across the regulator
PD = 0.808W TJ = TAMB + PD * TJA = 45 + 0.808W * 29C/W = 68.4C
Layout Guidelines One (or more) ground planes are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. The IC ground reference, VSSA, should be connected to PGND1 and PGND2 as a star connection at the thermal pad, which in connects using 4 vias to the ground plane. All components that are referenced to VSSA should connect to it directly on the chip side, and not through the ground plane. VDDQ: The feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. Route the feedback trace in a quiet layer if possible, from the output capacitor back to the chip. Chip supply decoupling capacitors (VCCA, VDDP) should be located next to the pins (VCCA/VSSA, VDDP/PGND1) and connected directly to them on the same side. VTT: Because of the high bandwidth of the VTT regulator, proper component placement and routing is essential to prevent unwanted high-frequency oscillations which can be caused by parasitic inductance and noise. The input capacitors should be located at the VTT input pins (VTTIN and PGND2), as close as possible to the chip to minimize parasitics. Output capacitors should be directly located at the VTT output pins (VTT and PGND2). The routing of the
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SC488
POWER MANAGEMENT Application Information (Cont.)
feedback signal VTTS is critical. The trace from VTTS (pin 2) should be connected directly to the output capacitor that is farthest from VTT (pin24); route this signal away from noise sources such as the VDDQ power train or highspeed digital signals. The switcher power section should connect directly to the ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). Power components should be placed to minimize loops and reduce losses. Make all the connections on one side of the PCB using wide copper fi lled areas if possible. Do not use "minimum" land patterns for power components. Minimize trace lengths between the gate drivers and the gates of the MOSFETs to reduce parasitic impedances (and MOSFET switching losses); the low-side MOSFET is most critical. Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling requirement (and to reduce parasitics) if routed on more than one layer. Current sense connections must always be made using Kelvin connections to ensure an accurate signal. The layout can be generally considered in three parts; the control section referenced to VSSA, the VTT output, and the switcher power section. Looking at the control section first, locate all components referenced to VSSA on the schematic and place these components at the chip. Connect VSSA using a wide (>0.020") trace. Very little current fl ows in the chip ground therefore large areas of copper are not needed. Connect the VSSA pin directly to the thermal pad under the device as the only connection from PGND1 and PGND2 from VSSA. Decoupling capacitors for VCCA/VSSA and VDDP/PGND1 should be placed is as close as possible to the chip. The feedback components connected to FB, along with the VDDQ sense components, should also be located at the chip. The feedback trace from the VDDQ output should route from the top of the output capacitors, in a quiet layer back to the FB components. Next, looking at the switcher power section, there are a few key guidelines to follow: 1. There should be a very small input loop, well decoupled. 2. The phase node should be a large copper pour, but still compact since this is the noisiest node. 3. Input power ground and output power ground should not connect directly, but through the ground planes instead. Finally, connecting the control and switcher power sections should be accomplished as follows: 1. Route VDDQ feedback trace in a "quiet" layer, away from noise sources. 2. Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to the chip using wide traces with multiple vias if using more than one layer. These connections are to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power ground as its return path. LX is the noisiest node in the circuit, switching between VBAT and ground at high frequencies, thus should be kept as short as practical. DH has LX as its return path. 3. BST is also a noisy node and should be kept as short as possible. 4. Connect PGND1 pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the ground plane. Locate the current limit resistor (if used) at the chip with a kelvin connection to the phase node.
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SC488
POWER MANAGEMENT Application Information (Cont.)
5V
D1 MBR0530
C1
0.1uF Q1 IRF7811 C2 10uF/25V 1210
VDDQ C4 1uF VTT C5 10uF 0805 C6 10uF 0805 C7 10uF 0805 Q2 IRF7832
21 24 22 23 20 19
L1 1.5uH Vishay IHLP-5050
VBAT C3 10uF/25V 1210
VDDQ R1 5.62K 18 17 16 15 14 13 PAD C12 1uF R4 10K PGOOD C9* + C10* + C11 0.1uF
C8 0.1uF
LX
BST
VTT
1 2 3
PGND2 VTTS VSSA TON REF VCCA
NC
VTTIN
DH
PGND1 U1 PGND1 ILIM VDDP VDDP
EN/PSV
DL
220uF/12m 220uF/12m *Sany o 4TPL220MC 5V
SC488 SC480
VBAT REF 5V
R2
1MEG R3 R5 C13 1nF 10R C14 1uF C15 1uF
4 10R 5 6
VDDQS
VTTEN
PGD
NC 12
FB
PAD
7
8
9
10
11
EN/PSV VTT_EN
VDDQ
C16 0.1uF
1.8V fixed: connect to 5V 2.5V fixed: connect to VSSA Adjustable 1.5V-3.0V: connect to divider netw ork
Figure 7 - Reference Design
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SC488
POWER MANAGEMENT Typical Characteristics
1.8V Efficiency vs. Output Current Powersave Mode
100%
VBAT = 10
1.8V Efficiency vs. Output Current Continuous Conduction Mode
100%
VBAT = 10
90%
90%
Efficiency (%)
80%
Efficiency (%)
VBAT = 20
VBAT = 20
80%
70%
70%
60%
60%
50% 0 2 4 6 8 10
50% 0 2 4 6 8 10
IOUT (A)
IOUT (A)
2.5V Efficiency vs. Output Current Powersave Mode
100%
VBAT = 10
2.5V Efficiency vs. Output Current Continuous Conduction Mode
100%
VBAT = 10
90%
90%
Efficiency (%)
Efficiency (%)
VBAT = 20
VBAT = 20
80%
80%
70%
70%
60%
60%
50% 0 2 4 6 8 10
50% 0 2 4 6 8 10
IOUT (A)
IOUT (A)
1.5V Efficiency vs. Output Current Powersave Mode
100%
VBAT = 10
100%
1.5V Efficiency vs. Output Current Continuous Conduction Mode
VBAT = 10
90%
90%
Efficiency (%)
80%
VBAT = 20
Efficiency (%)
80%
VBAT = 20
70%
70%
60%
60%
50% 0 2 4 6 8 10
50% 0 2 4 6 8 10
IOUT (A)
IOUT (A)
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SC488
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Transient Response, 0 to 5A, Psave Mode Load Transient Response, 0 to 5A, Continuous Conduction Mode
Load Transient Response, 5 to 0A, Psave Mode
Load Transient Response, 5 to 0A, Continuous Conduction Mode
Load Transient Response, 5 to 10A
Load Transient Response, 10 to 5A
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SC488
POWER MANAGEMENT Typical Characteristics (Cont.)
VTT Load Transient Response, 1A Sink/Source, Psave Mode VTT Load Transient Response, 1A Sink/Source, Continuous Conduction Mode
Startup (PSV), EN/PSV Going High
Startup (PSV), EN/PSV Going Low, VDDQ = 5A
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SC488
POWER MANAGEMENT Outline Drawing - MLPQ 24 (4x4mm)
A
D
B
DIM
A A1 A2 b D D1 E E1 e L N aaa bbb
SEATING PLANE A1 D1 LxN E/2 E1 2 1 N e D/2 C
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C
.031 .035 .040 .000 .001 .002 - (.008) .007 .010 .012 .151 .157 .163 .100 .106 .110 .151 .157 .163 .100 .106 .110 .020 BSC .011 .016 .020 24 .004 .004
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.85 4.00 4.15 2.55 2.70 2.80 3.85 4.00 4.15 2.55 2.70 2.80 0.50 BSC 0.30 0.40 0.50 24 0.10 0.10
bxN bbb CAB
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
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SC488
POWER MANAGEMENT Land Pattern - MLPQ 24 (4x4mm)
K
DIMENSIONS DIM C G H K P X Y Z INCHES (.155) .122 .106 .106 .021 .010 .033 .189 MILLIMETERS (3.95) 3.10 2.70 2.70 0.50 0.25 0.85 4.80
(C)
H
G
Z
X P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
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